Nowadays, the size for transistor is approaching to the nano domain. In the nano scale, the power supply voltage of chip is reduced; obviously, the reduction of device size not only makes the chip area smaller to save the silicon cost, but also the lower supply voltage will consume lower power. Thus, the chip design is rapidly migrating to the nano-scale low-voltage level for CMOS technology. However, some peripheral components and other ICs are still operating in high voltage level, such as 3.3V or 5V. In other words, the electric system has to provide with the chips operating in different voltages. In order for the compatibility of chips with different voltage levels, the input/output buffer in prior art was not suitable, and caused some problems, such as the reliability problem for gate oxide layer, deterioration of thermal carriers, and generation of undesired current leakage path.
FIG. 1 is a circuit diagram for the conventional tri-state input/output buffer in mixed-voltage interface. The input/output buffer was subjected to current leakage, and the reliability problem of gate oxide layer. In the receiving mode, the gate voltage for the pull-up P-type MOS transistor T1 and the pull-down N-type MOS transistor T2 in the conventional tri-state buffer was biased by the voltage VDD and the ground voltage GND conventionally, and employed the pre-driver U1 to close the pull-up P-type MOS transistor T1 and the pull-down N-type MOS transistor T2. During the receiving mode, the input signal at the input/output pad P11 is raised to two times of voltage VDD, the drain of the pull-up P-type MOS transistor T1 will be forwardly biased to the parasitic PN junction diode D1. Thus, the undesired current leakage path will penetrate the parasitic junction diode, and occur between the input/output pad P1 and the power supply voltage VDD. Moreover, because the gate voltage of the pull-up P-type MOS transistor T1 is biased at the voltage VDD, and the input signal at the input/output pad P11 is with the value two times of voltage VDD, the channel of the pull-up P-type MOS transistor T1 will be opened in the receiving mode to connect another undesired current leakage path from the input/output pad P11 to the power supply voltage VDD, and this undesired current leakage will not only cause more power consumption in the electric system, but also result in possible failure in the whole system. In order to avoid the reliability problem of the gate oxide layer, the devices with the gate oxide layer problems in some mixed input/output pads will replace the devices having overloaded gate oxide layer with the thick oxide layer device. However, it will increase the manufacturing cost for the chip having both the thick oxide layer devices and the thin oxide layer devices.
FIG. 2 is a circuit diagram showing conventional mixed-voltage input/output buffer, in which the transistors 107, 109 and 110 are used to generate the offset voltage to bias the gate of the transistor 108. However, the DC current path in the transistors 107, 109 and 110 existed from voltage VDD to voltage VSS will cause additional power consumption, and using the stacked transistors 101, 102 will reduce the driving capability.
FIG. 3 is a circuit diagram showing further another conventional mixed-voltage input/output buffer, which includes two stacked P-type MOS transistors having large silicon area. Moreover, the transistors 270, 280 using virtual diodes will generate the offset voltage to bias the bulk of the P-type MOS transistors 230, 260. The bulk voltage has a voltage drop. If the bulk voltage clamps the voltage VDD through the transistor 270 and the bulk voltage is resulted from the virtual diode structure, the voltage will be the voltage VDD minus the threshold voltage Vt, and this low body voltage will result in large amount of subthreshold current leakage of transistors 230, 260.
FIG. 4 is a circuit diagram showing a conventional mixed-voltage input/output buffer, in which the additional pad P41 and the additional offset voltage V41 (voltage of V41 is 5V) are used for the bulk of the biased P-type MOS transistor 401. Moreover, the P-type MOS transistor 401 is a thick oxide layer (high voltage) device for preventing the reliability problem of the gate oxide layer, which will result in more cost and larger silicon area. And, using high voltage (5V) for biasing the body will deteriorate the driving capacity of the transistor 402 due to the bulk bias effect.
FIG. 5 is a circuit diagram showing another conventional mixed-voltage input/output buffer. The current employs the feedback technique to control the voltage of the bulk 242 and the gate voltage of the transistor 232 for the P-type MOS transistor. When the buffer driving voltage VDD is the output voltage, the voltage of the body for the P-type MOS transistor is the bias current value VDD minus from the threshold voltage Vt, it will result in large amount of sub-threshold current leakage.
FIG. 6 is a circuit diagram showing another conventional voltage input/output buffer, in which the body voltage of the P-type MOS transistor 321 is the offset voltage VDD minus from the threshold voltage Vt. Moreover, when the input/output buffer is receiving a high input voltage, the base voltage of the P-type MOS transistor will be biased through the parasitic diode 322, and further result in the occurrence of large amount of sub-threshold current leakage.